工作內容
1. Integrate DDR controller/phy related IPs.
2. Analysis design and verify DDR controller/phy.
3. Maintain and improve ASIC design/verification environment.
4. Maintain DRAM Mass Production ICs and issue Tracking/debugging.
工作說明
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工作縣市:新北市
- 上班地點:新北市新店區
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工作待遇:面議
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上班時段:日班,
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需求人數:1
條件要求
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工作經歷:
2年以上
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學歷要求:碩士
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科系要求:
電機電子工程相關
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專長需求:
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擅長工具:
- 具備駕照:
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其他條件:
1. Familiar with SystemVerilog/UVM is a plus.
2. Familiar with ARM Bus Protocol is a plus.
3. Familiar with FE tools such as nLint/CDC/Code Coverage tool is a plus.
4. Familiar with perl/makefile/python language is a plus.
5. Effective interpersonal communication skills.
