工作內容
1. Develop the NVMe/PCIe Verification environment by System Verilog.
2. Verification and debug the high speed interface.
3. Built up block/system-level verification environment.
工作說明
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工作縣市:新竹縣市
- 上班地點:新竹縣竹北市
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工作待遇:面議
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上班時段:日班,
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需求人數:1
條件要求
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工作經歷:
3年以上
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學歷要求:碩士
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科系要求:
電機電子工程相關
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專長需求:
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擅長工具:
Verilog
- 具備駕照:
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其他條件:
1.Familiar with high speed (PCIE, USB, MIPI, SATA) protocol and architecture
2. Familiar with AMBA interface (AHB, APB, AXI) protocol.
3. Familiar with DDR protocol.
4. Knowledge and design experience of design verification such as UVM and system Verilog / Verilog.
