工作內容
1. Digital IC design
2. RTL coding / simulation
3. System integration
4. ASIC/FPGA verification
工作說明
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工作縣市:新北市
- 上班地點:新北市新店區
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工作待遇:面議
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上班時段:日班,
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需求人數:2
條件要求
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工作經歷:
3年以上
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學歷要求:碩士
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科系要求:
資訊工程相關
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專長需求:
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擅長工具:
- 具備駕照:
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其他條件:
1. Familiar Verilog RTL coding/ simulation.
2. Familiar with Design Compiler/PrimeTime/Prime Power/Conformal LEC.
3. Familiar with 28nm/12nm or advanced process.
4. Experience in FPGA verification.
5. Experience in AXI/AHB/APB protocol is a plus.
6. Experience in DMA is preferred.
7. Experience in encryption/decryption IP (AES/SHA/RSA/etc …) is preferred.
8. Experience in SMBus/I2C and NVMe-MI is preferred.
9. Experience in clock/reset/analog IP control is prefered.
